This invention relates in general to matrix arrays of electronic elements and more particularly to a partitioning arrangement for interconnecting an array of individual electronic elements into a readily expandable matrix.
In a number of electronic applications a matrix method is used to access one element out of many elements. The most historical application of this method is in memories. That is, a plurality of storage elements are interconnected to each other horizontally in rows and vertically in columns. Interconnecting buses running horizontally interconnect the rows while buses running vertically interconnect the columns. Typically, these buses are extended to a remote device via buffers (drivers and/or receivers) which are normally located at the ends of the buses.
This type of architecture does not readily lend itself to the expansion of the matrix by simply adding additional storage elements. The interconnection buses must be sized to a particular matrix size and the required amount of buffers physically added to the matrix to access each storage element. Therefore, a matrix of this type is normally designed and configured for maximum size. In designing such matrix arrays it would be more cost effective to start with a minimally sized matrix and add elements to the matrix as the needs of the system requires them.
Accordingly, it is the object of the present invention to provide a partitioning arrangement for interconnecting a plurality of individual electronic elements into a readily expandable matrix.